PCI Express X1 slots

PCI Express has the following advantages over PCI:

• Serial technology providing scalable performance.
• High bandwidth—Initially, 5-80 gigabits per second (Gbps) peak theoretical bandwidth, depending on the implementation.
• Point-to-point link dedicated to each device, instead of the PCI shared bus.
• Opportunities for lower latency (or delay) in server architectures, because PCI Express provides a more direct connection to the chip set Northbridge than PCI-X.
• Small connectors and, in many cases, easier implementation for system designers.
• Advanced features—Quality of service (QoS) via isochronous channels for guaranteed bandwidth delivery when required, advanced power management, and native hot plug/hot swap support.

PCI Express X16 Goldfingers versus AGP Goldfingers

PCI Express will replace the PCI, PCI-X, and AGP parallel buses gradually over the next decade. It will initially replace buses that need the additional performance or features. For instance, PCI Express will initially be deployed as a replacement for the AGP8X graphics bus in client systems, providing high bandwidth and support for multimedia traffic. It will also coexist with and ultimately replace the PCI-X bus in server systems.

PCI Bottlenecks and Downsides

The conventional PCI Bus only offers a throughput (maximum theoretical bandwidth) of 1.056Gbps while Serial-ATA hard drives can offer a maximum of 1.5Gbps (3.0Gbps with SATA II); however, if a SATA controller can only have a transfer rate of 1.056Gbps, the SATA drive will have a transfer rate of only 132MBps (megabytes per second), which is roughly equivalent to ATA-133 technology. This is true if there are no other peripherals requesting use of the bandwidth. PCI shares that 132MBps bandwidth as it only uses one PCI bus which is connected in parallel. Although there are other PCI versions available, most motherboards and components use the 32-bit PCI bus which operates at 33MHz.

Gigabit LAN cards use approximately 95% of the available PCI bus bandwidth. This leaves little room for any other peripherals to use bandwidth. Currently the primary user will be using the sound card, hard drive and LAN on the PCI bus, this could cause transfer issues, sound clipping and HD transfer interrupts.

PCI Express Is Not a Bus

PCI Express is not a bus. A bus is a data path where you can attach several devices at the same time, sharing this data path. PCI Express is a point-to-point connection, i.e. it connects only two devices and no other device can share this connection. Just to clarify, on a motherboard using standard PCI slots, all PCI slots are connected to the PCI bus and share the same data path. On a motherboard with PCI Express slots, each PCI Express slot is connected to the motherboard chipset using a dedicated lane, not sharing this lane (data path) with other PCI Express slots. In name of simplification, we are calling

PCI Express as a "bus", since for laymen “bus” is easily recognized as “data path between devices”.

PCI Versus PCI Express

Because PCI Express it is a point-to-point architecture, the entire bandwidth of each PCI Express bus is dedicated to the device at the end of the link. Multiple PCI Express devices can be active without interfering with each other. In contrast to PCI, PCI Express has minimal sideband signals and the clocks and addressing information are embedded in the data. Because PCI Express is a serial technology with few sideband signals, it provides a very high bandwidth per I/O connector pin compared to PCI. This is designed to result in more efficient, smaller, and cheaper connectors. .

PCI Express Architecture

The PCI Express link is built around a bidirectional, serial (1-bit), point-to-point connection known as a "lane". This is in sharp contrast to the PCI connection, which is a bus-based system where all the devices share the same unidirectional, 32-bit, parallel bus.

At the electrical level, each lane utilizes two unidirectional low voltage differential signaling (LVDS) pairs at 2.5 gigabaud. Transmit and receive are separate differential-pairs, for a total of 4 data wires per lane.

A connection between any two PCI Express devices is known as a "link", and is built up from a collection of 1 or more lanes. All devices must minimally support single-lane (x1) links. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for very good compatibility in two ways. A PCI Express card will physically fit (and work correctly) in any slot that is at least as large as it is (e.g. an x1 card will work in an x4 or x16 slot), and a slot of a large physical size (e.g. x16) can be wired electrically with fewer lanes (e.g. x1 or x8; however, it must still provide the power and ground connections required by the larger physical slot size). In both cases, the PCI Express link will negotiate the highest mutually supported number of lanes. It is not, however, possible for a device to operate in a slot that is physically smaller than it (eg. a x4 card cannot fit in a slot which is physically an x1 slot - though it could operate in a x4 slot wired with only 1 lane).

PCI Express sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency comparable to PCI (which has dedicated interrupt lines) can be maintained.

Data transmitted on multiple lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCI Express specification refers to this interleaving as "data striping". While requiring significant hardware complexity to synchronize (or deskew) the incoming striped data, striping can significantly increase the data-throughput of the link. (Due to packet protocol rules, striping may not necessarily reduce the latency of small data packets on a link.)

As with all high-speed serial transmission protocols, clocking information must be embedded in the signal. At the physical level, PCI Express utilizes the very common 8B/10B encoding scheme to ensure that long strings of ones or zeros are broken up enough that the receiver does not lose track of where the bit edges are. This coding scheme replaces 8 uncoded (payload) bits of data with 10 (encoded) bits of transmitted data, consuming 20% of the overall electrical bandwidth.

First-generation PCI Express is constrained to a single signaling-rate of 2.5 Gigabits/s. PCI-SIG plans future versions adding signaling rates of 5 and 10 Gigabit/s.

First-generation PCI Express is often quoted to support a data-rate of 250 MB/s (238 MiB/s) in each direction, per lane. This figure is a calculation from the physical signaling-rate (2500 Mbaud) divided by the encoding overhead (10bits/byte.) This means a 16 lane (x16) PCI Express card would then be theoretically capable of 250 * 16 = 4000 MB/s (3.7 GiB/s) in each direction. While this is correct in terms of data bytes, more meaningful calculations will be based on the usable data-payload rate which depends on the profile of the traffic, which is a function of the high-level (software) application and intermediate protocol levels.