64-bit PCI expansion slots on a motherboard |
The conventional 32-bit PCI bus is ideal for slower speed
peripherals such as sound cards, modems, and Fast Ethernet
cards, but for an enterprise application needing Ultra 320
SCSI, Fibre Channel, and Gigabit Ethernet cards, a 64-bit
PCI bus is the way to go. A 64-bit PCI bus provides higher
overall throughput for high-performance adapters and better
system efficiency by providing the same data in fewer PCI
clock cycles. A 66-MHz PCI bus doubles the data throughput
over the same amount of time. The benefits of both 64-bit
and 66-MHz PCI implementations are better PCI bus utilization,
better overall PCI bus efficiency, and a substantial increase
in PCI bus performance.
Bus Comparison
Chart
| Bus Type |
Bus Width |
Bus Speed |
MB/sec |
| ISA |
16 bits |
8 MHz |
16 MBps |
| EISA |
32 bits |
8 MHz |
32 MBps |
| VL-bus |
32 bits |
25 MHz |
100 MBps |
| VL-bus |
32 bits |
33 MHz |
132 MBps |
| PCI |
32 bits |
33 MHz |
132 MBps |
| PCI |
64 bits |
33 MHz |
264 MBps |
| PCI-X 66 |
64 bits |
66 MHz |
512 MBps |
| PCI-X 133 |
64 bits |
133 MHz |
1 GBps |
| AGP x1 |
32 bits |
66 MHz |
266 MB/s |
| AGP x2 |
32 bits |
66 MHz |
533 MB/s |
| AGP x4 |
32 bits |
66 MHz |
1.066 MB/s |
| AGP x8 |
32 bits |
66 MHz |
2.133 MB/s |
|
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Newer revisions of PCI added new features and performance
improvements, including a 66 MHz 3.3 V standard and 133 MHz
PCI-X which equates to 1-GBps (gigabyte per second)!
64-bit PCI variants
- PCI 2.2 allows for 66 MHz signalling (requires 3.3 volt
signalling) (peak transfer rate of 533 MB/s)
- PCI-X changes the protocol slightly and increases the
data rate to 133 MHz (peak transfer rate of 1066 MB/s)
- PCI-X 2.0 specifies a 266 MHz rate (peak transfer rate
of 2133 MB/s) and also 533 MHz rate, expands the configuration
space to 4096 bytes, adds a 16-bit bus variant and allows
for 1.5 volt signalling
PCI Architecture
Since the 32-bit PCI bus is currently able to transfer 133 MB/sec
of data less the overhead, what results from changing the bus
to 64 bit and 66 MHz? How are PCI bus cycles affected by 64-bit
transfers? What are the additions to the PCI bus for 64-bit
extensions?
PCI Bus Cycles
Address and data transfers are multiplexed over the same
lines on the PCI bus, the address is sent first and then the
data. A 32-bit PCI bus has 32 data lines and is able to do
32-bit data transfers and 32-bit memory addressing or 64-bit
addressing using two 32-bit PCI cycles known as Dual Address
Cycles (DAC).
 Memory
addressing is not what constrains the PCI bus or system performance.  32-bit
addressing allows access to 4 GB of memory--systems such as
SMP systems need to address more than this range of memory
(see the illustration below). More memory can be addressed
with 64-bit addressing in one PCI cycle or two 32-bit cycles
using DAC, with the first cycle sending the low address and
the second cycle sending the high address.
In the illustration to the right, notice the number of PCI
cycles it takes to send the same 128 bytes of data over a
32-bit PCI bus versus a 64-bit bus, assuming the PCI bus is
not interrupted. 64-bit PCI bus transactions are more efficient,
both for addressing and data, because the number of PCI cycles
is reduced to half.
64-Bit Extension Pins
A 64-bit exte nsion to the 32-bit bus architecture requires
an additional 39 signal pins which are AD[64::32], C/BE[7::4]#,
REQ64#, ACK64#, and PAR64.
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| 64-bit
PCI Golfinger Voltage Visual Comparison |
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As we said before, data and addressing are multiplexed over
the same pins, either AD[31::00] for 32 bits or AD[31::00] and
AD[64::32] for 64 bits. During an address phase, AD[64::32]
is used to send the upper 32-bits of a 64-bit address or during
a data phase, an additional 32-bits of data. To transfer a 64-bit
address in one PCI cycle using the 64-bit bus, you must use
the DAC command and assert REQ64#. (Asserting or deasserting
a signal means that a particular message is present or missing
on the line.) To transfer the additional 32-bits of data on
AD[64::32], REQ64# and ACK64# must be asserted. The Bus Command
and Byte Enable Commands are multiplexe
d over C/BE[7::4]# pins; Bus Commands are transferred during
the address phase and Byte Enable Commands during the data phase.
An even parity bit, PAR64, protects the AD[63::32] pins from
data corruption. PAR64 has the same timing as AD[63::32] but
is delayed by one clock cycle.64-bit transactions are negotiated
using a transaction between a master and a target asserting
REQ64# and ACK64#. Devices determine if they are connected to
a 64-bit bus by asserting or deasserting REQ64# when RST# is
deasserted. Only memory commands support 64-bit data transfers.
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| 64-bit
PCI Slot Voltage Visual Comparison |
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64-Bit Bus Benefits
Many factors play into overall system performance and affect
the industry's progress to 64-bit PCI. The 32-bit PCI bus
is not in itself slowing system performance. Peripheral devices
such as SCSI, IDE, and Fast Ethernet by themselves do not
use the full potential of the current PCI bus. Interaction
between the PCI bus, the Host Bridge, DRAM, and the CPU commonly
slow down PCI transfers.
Let's also consider the transactions in the system. The CPU
communicates with Dynamic Random Access Memory (DRAM) and
the Host Bridge: the Host Bridge in turn communicates with
the PCI bus and DRAM. Direct Memory Access (DMA) devices transfer
data directly to DRAM through the PCI bus as shown here.
The burst rate of data throughput on the PCI bus doubles
with 64-bit data transfers. 64-bit DMA devices can move data
in 64-bit chunks directly between the PCI bus and DRAM if
the PCI bus and DRAM are set up the handle 64-bit transfers.
The system with a 64-bit PCI bus is less congested; 64-bit
devices in the system get on and off the bus in half the time,
making the PCI bus more efficient. In essence, since 64-bit
transfers achieve better PCI bus utilization and more devices
can be added to the bus before realizing the bus' full bandwidth
potential. The more heavily weighted your system becomes with
peripheral devices the more it benefits from a 64-bit wide
PCI bus.
Notice in the following drawings, the number of components
that would be affected by increasing the PCI bus to 64-bits,
the host bridge, the DRAM, the CPU and even the OS and driver.
Since the majority of transactions are data transfers from
the PCI bus to DRAM and from DRAM to the PCI bus, you could
consider that increasing the bandwidth of the bus would increase
the performance of the system. However, the CPU and the OS
may become the bottleneck even if implementing a 64-bit PCI
bus.
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