A built-in watchdog timer resets the pod if, for some unexpected reason, the microcontroller "hangs up" or if the power supply voltage drops below 4.75 VDC. Data collected by the pod is stored in local RAM for later access through the computer's serial port. This feature facilitates a stand-alone mode of operation. For example, a portable or laptop computer that has an RS-485 port can be brought to the pod, connected, and collect the data.
There is a switchable current source on analog channel 0 that may be used to detect a burned-out or disconnected external sensor. This current source may be used to check that a sensor is OK before taking measurements from that sensor.
A delta-sigma converter consists of a sample/hold amplifier, a differential amplifier (subtractor, the delta part), an analog low-pass filter (integrator, the sigma part), a comparator, a 1-bit DAC, and a digital filter. The analog signal is applied to the subtractor along with the output of the l-Bit DAC. The subtractor output is applied to the low-pass filter and the low-pass-filtered output is, in turn, coupled to the comparator. The comparator output is samples of the difference signal at a frequency many times the Nyquist frequency. (The Nyquist frequency is equal to 2X the highest frequency present in the analog signal.) This process is called oversampling.
The delta-sigma converter in RAD242 samples the analog signal at 19.5 KHz or greater (depending on the gain selected). As a result, the quantization noise is spread over a wider frequency than the band of interest. The noise in the band of interest is reduced further by the low frequency filter. The output of the comparator provides the digital input to the 1-Bit DAC so that the system functions as a negative feedback loop that tries to minimize the difference signal. The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. If the analog signal is zero, the duty cycle is 50%. The duty cycle increases for a positive analog signal and decreases for a negative one. The digital filter removes noise injected during the conversion process. The output of the digital filter is a binary representation of the rolling average of the sampled signal.
This architecture is inherently monotonic (no missing codes) and provides very high accuracy but at the expense of measurement speed (data output rate). For example, to achieve 22 bits resolution, a 10 MHz clock rate would result in a data or measurement rate of less than 10 Hz. The processes of oversampling and then integrating the readings produces a fixed delay from the time that an analog sample is taken until the digital value is output. The amount of delay is dependent on the oversampling rate. In most signal processing applications this lag is not significant. However, for real-time control applications, this lag should be considered.
Calibration of RAD242 can be done in any of three ways:
a. System calibration.b. Self calibration of the A/D.c. Background calibration of the A/D.
System calibration requires application of zero volts and full-scale voltage to the pod's analog inputs. Self calibration of the A/D chip can be performed in software and uses the reference voltage. Background calibration of the A/D can be commanded in software to occur with each conversion. In the background-calibration mode, the calibration procedure is interleaved with the normal conversion sequence and reduces the conversion rate by a factor of six. Calibration constants are stored automatically in the EEPROM.
Post filtering can also be used to reduce the output noise for bandwidths below 2.62 Hz. At a gain of 128, the output RMS noise is 250 nV. This is essentially device noise or white noise, and since the converter uses a chopper-stabilized input stage to reduce input drift, the noise has a flat frequency response. By reducing the bandwidth below 2.62 Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of two results in a reduction in the output rms noise equal to the square root of two. This additional filtering will also result in a longer settling time.
The worst-case settling time of the filter for a full-scale step input change is four times the data rate. For example, with the first filter notch at 50 Hz, the full-scale step settling time of the filter would be 80 mS (maximum). Due to a digital signal processing method used by the delta-sigma converter in the RAD242, changing the channel gain (in addition to the output sample rate) impacts the resolution.
150 dB ±0.02 x ƒNOTCH min., for ƒNOTCH of 10,30, 60 Hz.
20µA nom., constant current source for thermocouple cold junction reference measurements.
4.5µA nom., switchable current source tied to the positive input lead of analog channel one to test the existence/ operation of any external sensor.
Precision 10 VDC (±0.01V) at up to 60 mA.
